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SPL02E1 SP
19.5KB LCD Controller/Driver 19
NOV. 08, 2002 Version 1.0
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice.
Information provided by SUNPLUS TECHNOLOGY CO. No responsibility is assumed by In addition, SUNPLUS products
is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may
SPL02E1
Table of Contents
PAGE
1. GENERAL DESCRIPTION...................................................................................................................................................................... 3 2. BLOCK DIAGRAM.................................................................................................................................................................................. 3 3. FEATURES ............................................................................................................................................................................................. 3 4. SIGNAL DESCRIPTIONS ....................................................................................................................................................................... 4 5. FUNCTIONAL DESCRIPTIONS.............................................................................................................................................................. 5 5.1. ROM AREA....................................................................................................................................................................................... 5 5.2. SYSTEM OPERATION MODE (R/W)...................................................................................................................................................... 5 5.3. INTERRUPT (R/W) ............................................................................................................................................................................. 5 5.4. LOW VOLTAGE RESET (LVRST).......................................................................................................................................................... 5 5.5. I/O PORT.......................................................................................................................................................................................... 5 5.5.1. IOA (R/W) ............................................................................................................................................................................. 5 5.5.2. IOB (R/W) ............................................................................................................................................................................. 5 5.6. LCD DISPLAY CONTROLLER ............................................................................................................................................................... 5 5.7. CONTROL BYTE OF I/O PORT AND LCD DUTY RATE PORT (W).............................................................................................................. 5 5.8. TONE AND NOISE............................................................................................................................................................................... 5 5.9. SPEECH PLAY CONTROL PORT (W)..................................................................................................................................................... 5 5.10.SPEECH PORT (R/W)......................................................................................................................................................................... 5 6. ELECTRICAL SPECIFICATIONS ........................................................................................................................................................... 6 6.1. ABSOLUTE MAXIMUM RATINGS ........................................................................................................................................................... 6 6.2. DC CHARACTERISTICS (VDD = 3.0V, TA = 25) ................................................................................................................................ 6 6.3. DC CHARACTERISTICS (VDD = 4.5V, TA = 25) ................................................................................................................................ 6 6.4. THE RELATIONSHIPS BETWEEN THE ROSC AND THE FOSC........................................................................................................................ 7 6.4.1. VDD = 3.0V, TA = 25 .......................................................................................................................................................... 7 6.4.2. VDD = 4.5V, TA = 25 .......................................................................................................................................................... 7 6.5. THE RELATIONSHIPS BETWEEN THE FCPU AND THE IOP ........................................................................................................................... 7 6.6. THE RELATIONSHIPS BETWEEN THE FCPU AND THE VDD........................................................................................................................ 7 7. APPLICATION CIRCUITS....................................................................................................................................................................... 8 7.1. APPLICATION CIRCUIT ........................................................................................................................................................................ 8 7.2. CURRENT MODE DAC SPEAKER DRIVER ............................................................................................................................................ 9 8. PACKAGE/PAD LOCATIONS ............................................................................................................................................................... 10 8.1. PAD ASSIGNMENT........................................................................................................................................................................... 10 8.2. ORDERING INFORMATION ................................................................................................................................................................. 10 8.3. PAD LOCATIONS ............................................................................................................................................................................. 11 9. DISCLAIMER........................................................................................................................................................................................ 12 10. REVISION HISTORY............................................................................................................................................................................. 13
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SPL02E1
19.5KB LCD CONTROLLER/DRIVER
1. GENERAL DESCRIPTION
The SPL02E1 is a CMOS 8-bit single chip micro-processor. With SUNPLUS state-of-the-art technology, it contains RAM, ROM, I/Os, one interrupt controller, two tone-generator, one noise generator, and one automatic display controller/driver. In addition, both PWM and current DAC audio outputs are provided in SPL02E1. the audio types through mask option. save the power. To reduce power
3. FEATURES
n Built-in 8-bit RISC processor n 192-byte SRAM n 19.5K-byte ROM n Max. CPU clock: 1.5MHz @ 4.5V n Widely operating voltage: 2.4V - 5.5V @ 1.5MHz n Built-in RC oscillator (only one resistor is needed) (mask option)
Depending on the application, users are welling to select one of
consumption, a software controllable standby switch is built-in to The SPL02E1 is a low cost but powerful IC that targets to fulfill various LCD application needs.
2. BLOCK DIAGRAM
8-BIT RISC PROCESSOR
19.5K x 8 PROG ROM 192 X 8 SRAM
40 SEGMENTS X 8 COMMONS LCD DRIVER
SEG40 - 1
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n One 7-bit D/A for audio output or PWM audio output n Provides standby function n Operating current (enable LVRST) PWM: 480mA (700KHz @ 4.5V) DAC: 720mA (700KHz @ 4.5V) In standby mode: ISTBY < 1mA n Rather low standby current
TIMER TIME BASE & INTERRUPT LOGIC
10 I/O P I N
PA0
n LCD matrix: 40 segments x 8 commons LCD bias: 1/4, 1/5 LCD duty: 1/4, 1/8
PKEY
PA7 - 1 PB1 - 0
n 2 tone channels and one noise channel for coding audio sound in n 10 general I/O pins for key input
SOUND GENERATOR (2 TONES 1 NOISE 1 SPEECH)
D / A
Mask Option
AUDP
P W M
AUDN
COM8 -1
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4. SIGNAL DESCRIPTIONS
Mnemonic SEG40 - 23 SEG22 - 1 COM8 - 1 PA7 - 0 PB1 - 0 ROSC RESET AUDP AUDN VDD VSS PIN No. 18 - 1 64 - 43 26 - 19 34 - 41 32 - 33 42 27 29 31 30 28 O I/O I/O I I O O I I LCD driver common output I/O port I/O port R-osc input, connect to VDD through resistor System reset input Type O LCD driver segment output Description
Current DAC audio output, or PWM audio output (Mask Option) PWM audio output Power input Ground input
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5. FUNCTIONAL DESCRIPTIONS
5.1. ROM Area
$0000 $002F $0030 $00BF $00C0 $00FF $0100 $01FF $0200 $05FF $0600 $0FFF $1000 $1FFF $2000 $2FFF $3000 $3FFF $4000 $4FFF $5000 $5FFF $6000
$6FFF $7000 $7FFF
5.5. I/O Port
LCD Display RAM Area
SRAM for CPU Data
I/O & Control Register
Unused
SUNPLUS's Test Program
Program Bank
5.5.1. IOA (R/W)
b7, 6, 5, 4 -nibble 1 b3, 2, 1, 0 -nibble 0
5.5.2. IOB (R/W)
b1, 0 -nibble 2
Program / Data Bank 0
Unused
Program / Data Bank 1
Unused
Program / Data Bank 2
Unused
Program / Data Bank 3
To access ROM, users should program the BANK SELECT Register ($D7) first and then access the bank #1, #2, or bank #3 by addressing the higher bank to fetch data.
5.2. System Operation Mode (R/W)
options.
The SPL02E1 provides normal mode and standby mode for user's
5.3. Interrupt (R/W)
1). 2Hz interrupt 2). Sound generator 3). Power key
The SPL02E1 provides three interrupt sources
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5.6. LCD Display Controller
SPL02E1.
Interrupt Vectors
There are total of 8 commons and 40 segments available in the The 40-byte SRAM are allocated at $00-$2Fh for displaying LCD data.
5.7. Control Byte of I/O Port and LCD Duty Rate Port (W)
1). Set IOA, IOB as input status or output status 2). Set LCD duty
3). Set CPU clock rate: non-divided or divided-by-8
5.8. Tone and Noise
generator.
The SPL02E1 provides two tone-generator and one noise Totally, 10 bits are used for programming the tone Two types of noise can be chosen and one register frequency, and two registers for controlling the amplitude of ToneA and ToneB. can be used to control the amplitude of noise.
5.9. Speech Play Control Port (W)
b0 = 0:non play mode 1:speech play mode
5.10. Speech Port (R/W)
In speech play mode, once data is written to the speech port, it is pumped to speaker through D/A or PWM (mask option) converter. The bit7 is a sign bit; `0' represents positive data and `1' represents negative data. The bit0 to bit5 are magnitude bits
5.4. Low Voltage Reset (LVRST)
The SPL02E1 provides a low voltage reset function. Once LVRST function is enabled (by mask option), the entire system will enter into RESET state if and only if the power supply voltage VDD is lower than 2.2V (typical).
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6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
Symbol V+ VIN TA TSTO
Ratings < 7.0V -0.5V to V+ + 0.5V 0 to +60 -50 to +150
For normal operational
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
6.2. DC Characteristics (VDD = 3.0V, TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Symbol VDD IOP Limit Min. 2.4 Typ. Max. 3.6 -
Audio output current Input High Level Input Low Level Output High I Output Sink I
6.3. DC Characteristics (VDD = 4.5V, TA = 25)
Characteristics Operating Voltage Operating Current Standby Current Symbol VDD IOP
Audio output current Input High Level Input Low Level Output High I Output Sink I
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380 mA ISTBY IOH IOL 1.0 mA -35 40 mA mA V VIH VIL 2.0 0.8 V IOH IOL -1.0 1.1 mA mA Limit Typ. Min. 3.6 Max. 5.5 Unit V 720 mA ISTBY IOH IOL 1.0 mA - 45 50 mA mA V VIH VIL 2.4 0.8 V IOH IOL -1.3 1.4 mA mA
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Test condition
For 2-battery application
VDD = 3.0V, FCPU = 700KHz
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VDD = 3.0V VDD = 3.0V, VOH = 2.0V
VDD = 3.0V, VOL = 0.8V VDD = 3.0V VDD = 3.0V VDD = 3.0V, VOH = 2.0V
VDD = 3.0V, VOL = 0.8V
Test condition
For 3-battery application VDD = 4.5V, FCPU = 700KHz
VDD = 4.5V VDD = 4.5V, VOH = 3.5V
VDD = 4.5V, VOL = 0.8V VDD = 4.5V VDD = 4.5V VDD = 4.5V, VOH = 3.5V
VDD = 4.5V, VOL = 0.8V
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6.4. The Relationships between the ROSC and the FOSC 6.4.1. VDD = 3.0V, TA = 25 6.5. The Relationships between the FCPU and the IOP
1.5 FCPU ( MHz ) 1.0 0.5
I OP ( m A )
1.0
VDD = 4.5V
0.5 VDD = 3V 0.0
0.0 0 200 400 Rosc ( Kohms ) 600 800
0.0
0.5
6.4.2. VDD = 4.5V, TA = 25
6.6. The Relationships between the FCPU and the VDD
1.5 FCPU ( MHz ) 1.0 0.5 0.0 0
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F CPU ( MHz ) 1.5 1.0 0.5 0.0 2.0 3.0 4.0
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Rosc = 150 Kohms Rosc = 220 Kohms
5.0
200
400
600
800
Rosc ( Kohms )
VDD ( Volts )
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SPL02E1
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SEG[40:1]
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SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38
SEG39 SEG40 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 RESET
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SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7
LCD Module
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SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
SPL02E1 Application CKT
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(LCD 1/4 or 1/5 Bias is Mask Option)
ROSC
ROSC
SPL02E1
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
ON/OFF KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 KEY7
VSS AUDP VDD AUDN PB1 PB0
COM[8:1]
AUDP VDD VDD VDD
VDD
ROSC
R1
SP
SP
7. APPLICATION CIRCUITS
DC=4.5V
7.1. Application Circuit
RESET KEY
C1
20p
0.1mF
C3 0.1 mF
0.1 mF
DAC PWM Output Output
(c) Sunplus Technology Co., Ltd. Proprietary & Confidential
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+C - 2.2 mF
4
250K
Q2 C2
R2 1K
AUDN
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7.2. Current Mode DAC Speaker Driver
C1: 0.1mF ~ 1mF RB1: 680 ~ 1.5K 4W ~ 8 W
VDD
RB1: 10K ~ 50K RB2: 820 ~ 1.5K C1: 0.1mF ~ 1mF 32 W ~ 64 W
VDD
AUD C1 RB1
8050
AUD RB2
RB1 C1
Figure 1 VDD
RB1: 2K~10K; C1: 1mF ~ 10mF RB2: ~1K; C2: ~0.1mF
AUD RB2
RB1: ~ 360 W (Vol) RB2: ~ 4.7 W AUD
1N4148
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RB2: ~1K; Enable C2: ~0.1mF 4W ~ 64 W C2 RB1 RB1 8050 AUD C1 RB2 C1 Figure 3 Figure 4 VDD Power 6 4W ~ 64 W AUDP 3 LM386 4 5 2 7 8050 RB1 RE1 20K RB1 Figure 5 Figure 6
RB1: 2K~10K; C1: 1 m F~10 mF
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C2
8050
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8050
VDD
4W ~ 8 W
220 mF + 10
0.1 mF 0.01 mF
Figure 1: The simplest CKT uses a low impedance speaker. It has high operation current, but the cost is the cheapest. Figure 2: It is the same as Figure 1 but a high impedance speaker is used. Figure 3: The CKT contains a low pass filter. It is capable of providing higher speech quality, but it always takes higher operation current. Figure 4: Improved version of Figure 3. The standby current can be controlled by the enable pin. Figure 5: The current mirror mode. It is able to control the volume. In addition, it is more stable and has lower operation current than Figure 1-3. Figure 6: High quality, low operation current CKT, but more expensive.
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8. PACKAGE/PAD LOCATIONS
8.1. PAD Assignment
Note1: Chip size included scribe line.
Note2: To ensure that the IC functions properly, please bond all of VDD and VSS pins.
Note3: The 0.1mF capacitor between VDD and VSS should be placed to IC as close as possible.
8.2. Ordering Information
Note1: Code number (nnnnV) is assigned for customer.
Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z).
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Chip Size: 2210mm x 1990mm This IC substrate should be connected to VSS
Product Number Package Type
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SPL02E1-nnnnV-C
Chip form
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8.3. PAD Locations
PAD No. PAD Name X Y PAD No. PAD Name X Y
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8
-963 -963 -963 -963 -963 -963 -963 -963 -963 -963 -963 -963 -963 -963 -963 -963 -837 -716
855 729 610 495 385 275 165 55 -55 -165 -275 -385 -495 -610 -729 -855 -855 -855
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PB0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
977 977 977 977 977 977
-855 -729 -610 -495 -385 -275 -165
RESET VSS
AUDP VDD
AUDN PB1
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SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 -598 -488 -378 -268 -158 -48 62 -855 -855 -855 -855 -855 51 52 53 54 55 SEG9 SEG10 SEG11 SEG12 SEG13 -855 56 57 SEG14 62 -855 SEG15 172 -855 58 SEG16 282 392 502 612 -855 -855 59 60 SEG17 SEG18 -855 -855 61 62 SEG19 SEG20 730 -855 63 SEG21 851 -855 64 SEG22
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ROSC
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977 977 977 977 977 977 977 977 977 977 851 730 612
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-55 55 165 275 385 495 610 729 855 855 855 855 855 855 855 855 855 855 855 855 855 855 855 855 855
502 392
282 172
-48
-158 -268 -378 -488 -598 -716
-837
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9. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SUNPLUS reserves the right to halt production or alter the specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. publication are current before placing orders.
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only.
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10. REVISION HISTORY
Date Revision # Description Page
NOV. 08, 2002
1.0
Original
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